~90 synthesizable SystemVerilog files (IEEE 1800-2017) with the full verification environment: UVM and Verilator flows, conformance harnesses against HM and JM, Yosys synthesis scripts characterized at 12.8M NAND2-eq (~4.3 mm² logic at 22nm), and the complete doc tree — FVP, datasheet, integration and FPGA porting guides. Perpetual license, royalty-free option, right to modify.
“We're not selling code. We're selling the certainty that someone else has already paid the tuition.”
The power & area whitepaper and datasheet: per-resolution power tables, area breakdown by subsystem, DVFS operating points, coverage summary and the disclosed-gaps list. Distributed under NDA — see the boilerplate mutual NDA.